1. Field
Embodiments relate to a method and system for estimating a read level, a memory controller therefor, and a recording medium.
2. Description of the Related Art
There has been a lot of research into multi-level memory for storing multi-bit data in a single memory cell in order to increase the degree of integration in memory. Multiple bits, i.e., at least two bits can be stored in a memory cell of a multi-level memory device. Such memory cell that stores multiple bits is referred to as a multi-level cell (MLC) while a memory cell storing a single bit is referred to as a single-level cell (SLC). The threshold voltage distribution of a MLC changes over time due to coupling effect, charge loss, or the like. For this reason, it is desirable to relatively accurately estimate a read level in a non-volatile memory device in order to minimize a bit error rate (BER).
A variety of algorithms have been proposed for estimation of a read level. Algorithms aimed at decreasing a BER usually have a problem in that speed performance decreases due to the increase in the number of reads and data transfer in a memory device. When an algorithm is designed to minimize the decrease of the speed performance in order to overcome this problem, reliability may be decreased, increasing a BER. Therefore, a method of estimating a read level considering both a BER and speed performance is desired.